Portable highly integrated systems on chip (SOC) comprising analog, digital and radio frequency circuits have placed stringent requirements on power dissipation, chip area and performance of sub-systems such as ADC's (analog-to-digital converter) operating under noisy SOC environment. Advanced nano-technology manufacturing nodes have enabled reduction in logic delay, power consumption and chip area. This has immensely benefited successive approximation register (SAR) ADC topology due to its highly digital nature. It is quite challenging to design a single channel SAR ADC with 10 bits resolution and over 100 MSps with good linearity and dynamic performance. Time interleaving and pipeline architecture are typically used to enhance speed for a medium resolution ADC design. However, time interleaving requires additional calibration circuits for correcting channel mismatch and stringent clock jitter specification which trickles down to specifications of the phase-locked loop design, responsible for generating ADC clock and the clock distribution network. A pipeline ADC suitable for latency tolerant application has its own challenges for deep sub-micron CMOS (complementary metal-oxide-semiconductor) technology nodes such as designing the power hungry inter-stage residue amplifier operating at lower supply voltages which requires special op-amp design techniques/architectures to achieve the desirable gain. Multiple op-amp stages may have to be cascaded to achieve the desired gain since cascading transistors is not feasible.
Advances in DAC (digital-to-analog converter) switching schemes, high speed dynamic latch comparators, asynchronous timing logic, SAR logic and redundancy have further pushed the speed envelope while achieving low figure of merit. The capacitive DAC (CDAC) poses a significant speed bottle neck, affecting settling behavior and resulting in erroneous conversion result. A 10 bit capacitive DAC (CDAC) requires 7.63 τ time constants for the voltage to settle within a precision of ½ LSB. Only 250 psec is available for DAC settling time for a 150 MSps 10 bits data converter. Additionally, noise coupling from supply rails and DAC reference voltages results in erroneous conversion and degrades dynamic performance. Introducing redundancy and error correction capabilities is beneficial to preserve the dynamic performance of data converters, especially the ones operating within a system on chip's noisy environment.
Complex CDAC architecture including split capacitor, compensative capacitors and asymmetric CDAC metal routing to implement binary and non-binary redundancy methods used to relax DAC settling time limits the DAC resolution, unit capacitor size, capacitor charge transfer time and necessitates additional DAC calibration circuits. Adding redundancy requires additional bit cycles, complex control logic overhead, decoders, shifting input range and complex error correction logic to convert additional redundancy-induced bit cycles output to the required resolution.
Some of the issues or problems related to known devices are as described below.                A typical high performance, safety critical data converter operating in an automotive, System on Chip (SOC) (with analog, digital, radio operation—a typical internet of things (IOT) product) and industrial application is usually plagued with a noisy environment, which affects the operation of an analog-to-digital converter (ADC) causing incorrect digitized results and degraded signal to noise ratio and spurious free dynamic range.        Automotive companies SOC usually overdesign a typical data converter in terms of the resolution (bits) required such that the effective number of bits can meet the safety standards specified by the automotive standards body. With the commercialization push for all electric vehicles and driverless cars, more reliable and energy efficient data converters that can operate in a noisy SOC environment are required.        In some cases, multiple data converters are used for applications such as air bag deployment in a car. Error correction data converters without latency or additional cycles (N+X cycles, where X is additional cycles) for an N bit data converter is a desirable.        In a typical high speed data converter application, a number of parameters such as the digital-to-analog converter (DAC) voltage settling time, comparator regeneration and reset time, control logic delay to switch appropriate weights in a DAC are crucial.        The main challenge for any DAC is the voltage reference settling time, which should settle within less than ½ least significant bit (LSB). Failing which an error is caused in the analog converted digital value for a data converter without redundancy and error correction capability.        In general, sufficient time is allocated for the DAC to settle within VREFp±½ LSB. This leads to a speed bottleneck.        Redundancy can be implemented by either using a binary or non-binary approach. These approaches often require DAC splitting, extra DAC capacitors to add redundancy, hence increasing the control logic complexity which leads to increase in chip area, power consumption and reduced conversion speed. A non-binary implementation uses redundancy in all cycles including the first cycle. A non-binary scaled DAC implemented using thermometer code requires a decoder and 2×2N switches. Hence, area and power consumption are increased.        Complex high speed single-bit/multi-bit per cycle error correction SAR ADC requires power hungry arithmetic units utilizing shifters, subtractors, adders, multiplexers etc.        The unit capacitor matching of a capacitive DAC sets the total size of a DAC, hence defining the energy minima of the SAR ADC. Capacitor matching is limited with the technology used and is better for lower technology nodes (28 nm and below) as the manufacturing process utilizes dual masks for lithography and better Kσ which is the matching coefficient. These technology nodes are extremely costly and capacitor mismatch in DAC degrades the linearity (INL-Integral non linearity, and DNL-Dynamic non linearity) of the ADC. DAC mismatch is one of the important parameters that determines the manufacturing yield of a data converter. Hence a large unit capacitor leading to a large capacitive DAC size is preferred for commercial applications.        Mismatch in the capacitor leads to possible loss in linearity (INL and DNL). Additional cycles are required to achieve a 10-bit resolution. In one known implementation, 13 cycles are required to achieve a 12.7% redundancy margin.        In one known implementation, selective redundancy cycles are employed using a preprogrammed amount of redundancy cycles that can be used for error correction. Here, the amount of redundancy cycles determines the number of erroneous decisions that can be corrected. In total, N+X cycles are required to achieve a N-bit resolution (where X is the amount of extra redundancy cycles introduced).        